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freescale semiconductor, inc., 2009. all rights reserved. preliminary subject to change without notice this document contains information on a product under development. freescale reserves the right to change or discontinue this product without notice. 64-lqfp case 840f 48-lqfp case 932 48-qfn 1314 features 8-bit hcs08 central processor unit (cpu) up to 20-mhz cpu at 3.6v to 1.8v across temperature range of -40?c to 85?c hc08 instruction set with added bgnd instruction support for up to 32 interrupt/reset sources on-chip memory dual array flash read/program/erase over full operating voltage and temperature random-access memory (ram) security circuitry to prevent unauthorized access to ram and flash contents power-saving modes two low power stop modes reduced power wait mode low power run and wait modes allow peripherals to run while voltage regulator is in standby peripheral clock gating register can disable clocks to unused modules, thereby reducing currents. very low power external oscillator that can be used in stop2 or stop3 modes to provide accurate clock source to real time counter 6 usec typical wake up time from stop3 mode clock source options oscillator (xosc) ?loop-control pierce oscillator; crystal or ceramic resonator range of 31.25 khz to 38.4 khz or 1 mhz to 16 mhz internal clock source (ics) ?internal clock source module containing a frequency-locked-loop (fll) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports bus frequencies from 1mhz to 10 mhz. system protection watchdog computer operating properly (cop) reset with option to run from dedicated 1-khz internal clock source or bus clock low-voltage warning with interrupt low-voltage detection with reset or interrupt illegal opcode and illegal address detection with reset flash block protection development support single-wire background debug interface breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) on-chip in-circuit emulator (ice) debug module containing three comparators and nine trigger modes. eight deep fifo for storing change-of-?w addresses and event-only data. debug module supports both tag and force breakpoints peripherals lcd ?4x28 or 8x24 lcd driver with internal charge pump and option to provide an internally regulated lcd reference that can be trimmed for contrast control. adc 8-channel, 12-bit resolution; 2.5 ms conversion time; automatic compare function; temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6v to 1.8v acmp ?analog comparator with selectable interrupt on rising, falling, or either edge of comparator output; compare option to ?ed internal bandgap reference voltage; outputs can be optionally routed to tpm module; operation in stop3 sci ?full duplex non-return to zero (nrz); lin master extended break generation; lin slave extended break detection; wake up on active edge spi ?full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; msb-?st or lsb-?st shifting iic ?iic with up to 100 kbps with maximum bus loading; multi-master operation; programmable slave address; interrupt driven byte-by-byte data transfer; supports broadcast mode and 10-bit addressing tpmx two 2-channel (tpm1 and tpm2); selectable input capture, output compare, or buffered edge- or center-aligned pwm on each channel; tod ?(time of day) 8-bit quarter second counter with match register; external clock source for precise time base, time-of-day, calendar or task scheduling functions; free running on-chip low power oscillator (1 khz) for cyclic wake-up without external components. input/output 38 gpios, 2 output-only pins 8 kbi interrupts with selectable polarity hysteresis and con?urable pull up device on all input pins; con?urable slew rate and drive strength on all output pins. package options 64-lqfp, 48-lqfp and 48-qfn freescale semiconductor data sheet: advance information document number: MC9S08LL16 rev. 3, 01/2009 MC9S08LL16 series covers: MC9S08LL16 and mc9s08ll8 an energy efficient solution by freescale
MC9S08LL16 series, rev. 3 preliminary subject to change without notice freescale semiconductor 2 revision history to provide the most up-to-date information, the revision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com/ the following revision history table summarizes changes contained in this document. rev date description of changes 1 9/2008 initial release. 2 10/2008 updated electrical characteristics. 3 01/2009 corrected 48-pin qfn/lqfp pinouts for pins 29, 30, 32, and 32 in figure 3 . extracted stop mode adders from the supply current table and created a separate table for the data (see ta b l e 1 9 ). added missing power consumption parameters in supply current characteristics ( ta b l e 1 8 ). related documentation find the most current versions of all documents at: http://www.freescale.com reference manual (MC9S08LL16rm) contains extensive product information including modes of operation, memory, resets and interrupts, register de?ition, port pins, cpu, and all module information. 1 devices in the MC9S08LL16 series . . . . . . . . . . . . . . 3 2 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 parameter classification . . . . . . . . . . . . . . . . . . . 8 3.3 absolute maximum ratings. . . . . . . . . . . . . . . . . 9 3.4 thermal characteristics. . . . . . . . . . . . . . . . . . . 10 3.5 esd protection and latch-up immunity . . . . . . 11 3.6 dc characteristics. . . . . . . . . . . . . . . . . . . . . . . 12 3.7 supply current characteristics . . . . . . . . . . . . . 16 3.8 external oscillator (xoscvlp) characteristics 19 3.9 internal clock source (ics) characteristics . . . 20 3.10 ac characteristics. . . . . . . . . . . . . . . . . . . . . . . 23 3.10.1control timing . . . . . . . . . . . . . . . . . . . . . 23 3.10.2tpm module timing . . . . . . . . . . . . . . . . 24 3.10.3spi timing. . . . . . . . . . . . . . . . . . . . . . . . 25 3.11 analog comparator (acmp) electricals . . . . . . 28 3.12 adc characteristics . . . . . . . . . . . . . . . . . . . . . 28 3.13 lcd specifications . . . . . . . . . . . . . . . . . . . . . . 32 3.14 flash specifications . . . . . . . . . . . . . . . . . . . . 32 3.15 emc performance. . . . . . . . . . . . . . . . . . . . . . . 33 3.15.1radiated emissions . . . . . . . . . . . . . . . . 33 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.1 device numbering system . . . . . . . . . . . . . . . . 35 5 package information and mechanical drawings . . . . 35 table of contents
devices in the MC9S08LL16 series MC9S08LL16 series, rev. 3 preliminary subject to change without notice freescale semiconductor 3 1 devices in the MC9S08LL16 series table 1 summarizes the feature set available in the MC9S08LL16 series series of mcus. t the block diagram in figure 1 shows the structure of the MC9S08LL16 series mcu. table 1. MC9S08LL16 series features by mcu and package feature MC9S08LL16 mc9s08ll8 package 64-pin lqfp 48-pin qfn/lqfp 48-pin qfn/lqfp flash 16,384 (dual 8k arrays) 10,240 (8k and 2k arrays) ram 2080 2080 2080 acmp yes yes yes adc 8-ch 8-ch 8-ch iic yes yes yes irq yes yes yes kbi 8 8 8 sci yes yes yes spi yes yes yes tpm1 2-ch 2-ch 2-ch tpm2 2-ch - - tod yes yes yes lcd 8x24 4x28 8x16 4x20 8x16 4x20 i/o pins 1 1 i/o does not include two output-only port pins. 38 31 31
MC9S08LL16 series, rev. 3 preliminary subject to change without notice devices in the MC9S08LL16 series freescale semiconductor 4 figure 1. MC9S08LL16 series block diagram 8-bit keyboard interrupt ( kbi ) iic module ( iic ) serial peripheral interface ( spi) user flash b user ram on-chip ice debug module ( dbg) (ll16 = 8k bytes) hcs08 core cpu bkgd int bkp 2-channel timer/pwm ( tpm1 ) hcs08 system control resets and interrupts modes of operation power management cop irq lvd low-power oscillator internal clock source ( ics) serial communications 2-channel timer/pwm ( tpm2) (ll8 = 2k bytes) v ll1 v lcd lcd v ll2 v ll3 v cap1 v cap2 lcd[31:0] v ss v dd voltage regulator user flash a (ll8 = 8k bytes) ptc7/irq/tclk ptc5/tpm2ch1 ptc4/tpm2ch0 ptc3/tpm1ch1 port b ptb5/mosi/scl ptb4/miso/sda ptb3 ptb2/ reset ptb1/xtal ptb0/extal pta7/kbip7/adp7/acmp pta6/kbip6/adp6/acmp+ pta4/kbip4/adp4/lcd30 interface ( sci ) ptb7/ ss ptb6/spsck ptc1/txd ptc0/rxd txd rxd ss spsck scl sda mosi miso v ssa /v refl v dda /v refh xtal extal irq kbi[7:0] port a reset tpm2ch0 liquid crystal display driver analog-to-digital converter ( adc) 12-bit analog comparator ( acmp ) acmp+ acmp ad[7:0] time of day module ( tod ) tpm2ch1 tclk tpm1ch0 tpm1ch1 tclk pta1/kbip1/spsck/adp1 port c port d port e ptd[7:0]/lcd[7:0] pte[7:0]/lcd[15:8] ptc6/acmpo//bkgd/ms ptc2/tpm1ch0 pins not available on 48-pin packages. notes: when ptb2 is con?ured as reset, pin becomes bi-directional with output being open-drain drive containing an internal pull-up device. (ll16 = 8k bytes) (ll8 = 2k bytes) (ll16 = 2k bytes) pta5/kbip5/adp5/lcd31 lcd[23:16] not available on 48-pin packages. acmpo bkgd/ms when ptc6 is con?ured as bkgd, pin becomes bi-directional. k ey : pta0/kbip0/ ss/adp0 pta2/kbip2/sda/miso/adp2 pta3/kbip3/scl/mosi/adp3
pin assignments MC9S08LL16 series, rev. 3 preliminary subject to change without notice freescale semiconductor 5 2 pin assignments this section shows the pin assignments for the MC9S08LL16 series devices. figure 2. 64-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64-pin lqfp pte2/lcd10 pte3/lcd11 pte4/lcd12 pte5/lcd13 pte6/lcd14 pte7/lcd15 lcd16 lcd17 lcd18 lcd19 lcd20 lcd21 lcd22 lcd23 lcd24 lcd25 pte1/lcd9 pte0/lcd8 ptd7/lcd7 ptd6/lcd6 ptd5/lcd5 ptd4/lcd4 ptd3/lcd3 ptd2/lcd2 ptd1/lcd1 ptd0/lcd0 v cap1 v cap2 v ll1 v ll2 v ll3 v lcd pta6/kbip6/adp6/acmp+ pta7/kbip7/adp7/acmp v ssa/ v refl v dda /v refh ptb0/extal ptb1/xtal v dd v ss ptb2/ reset ptb3 ptb4/miso/sda ptb5/mosi/scl ptb6/spsck ptb7/ ss ptc0/rxd ptc1/txd 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 lcd26 lcd27 lcd28 lcd29 pta5/kbip5/adp5/lcd30 pta4/kbip4/adp4/lcd31 pta3/kbip3/scl/mosi/adp3 pta2/kbip2/sda/miso/adp2 pta1/kbip1/spsck/adp1 pta0/kbip0/ ss/adp0 ptc7/irq/tclk ptc6/acmpo/bkgd/ms ptc5/tpm2ch1 ptc4/tpm2ch0 ptc3/tpm1ch1 ptc2/tpm1ch0 note: v refh /v refl are internally connected to v dda /v ssa . 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
MC9S08LL16 series, rev. 3 preliminary subject to change without notice pin assignments freescale semiconductor 6 figure 3. 48-pin qfn/lqfp ptd0/lcd0 1 2 3 4 5 6 7 8 ptd3/lcd3 v dd ptb1/xtal ptb0/extal v dda /v refh v ssa/ v refl pta7/kbip7/adp7/acmp pta6/kbip6/adp6/acmp+ ptc7/irq/tclk ptc3/tpm1ch1 lcd26 pte7/lcd15 lcd24 lcd25 31 30 29 28 27 26 14 15 17 18 19 37 3839 13 24 25 36 48 9 10 11 v cap1 12 v ll2 v ss 20 ptb2/ reset 21 ptc0/rxd 22 23 ptc6/acmpo/bkgd/ms pte6/lcd14 40 pte5/lcd13 41 pte4/lcd12 42 pte3/lcd11 43 ptd2/lcd2 v cap2 v ll1 32 33 34 35 pte1/lcd9 47 46 45 pte2/lcd10 44 ptd5/lcd5 ptd4/lcd4/ v ll3 ptc2/tpm1ch0 lcd27 48-pin qfn/lqfp note: v refh /v refl are internally connected to v dda /v ssa ptd1/lcd1 ptd7/lcd7 ptd6/lcd6 pta5/kbip5/adp5/lcd30 pta4/kbip4/adp4/lcd31 pta0/kbip0/ ss/adp0 pta1/kbip1/spsck/adp1 pta3/kbip3/scl/mosi/adp3 pta2/kbip2/sda/miso/adp2 lcd28 lcd29 pte0/lcd8 ptc1/txd 16
pin assignments MC9S08LL16 series, rev. 3 preliminary subject to change without notice freescale semiconductor 7 table 2. pin availability by package pin-count <-- lowest priority --> highest 64 48 port pin alt 1 alt 2 alt3 alt4 1 47 pte1 lcd9 2 48 pte0 lcd8 3 1 ptd7 lcd7 4 2 ptd6 lcd6 5 3 ptd5 lcd5 6 4 ptd4 lcd4 7 5 ptd3 lcd3 8 6 ptd2 lcd2 9 7 ptd1 lcd1 10 8 ptd0 lcd0 11 9 v cap1 12 10 v cap2 13 11 v ll1 14 12 v ll2 15 13 v ll3 16 v lcd 17 14 pta6 kbip6 adp6 acmp+ 18 15 pta7 kbip7 adp7 acmp 19 16 v ssa v refl 20 17 v refh v dda 21 18 ptb0 extal 22 19 ptb1 xtal 23 20 v dd 24 21 v ss 25 22 ptb2 reset 26 ptb3 27 ptb4 miso sda 28 ptb5 mosi scl 29 ptb6 spsck 30 ptb7 ss 31 23 ptc0 rxd 32 24 ptc1 txd 33 25 ptc2 tpm1ch0 34 26 ptc3 tpm1ch1 35 ptc4 tpm2ch0 36 ptc5 tpm2ch1 37 27 ptc6 acmpo bkgd ms 38 28 ptc7 irq tclk
MC9S08LL16 series, rev. 3 preliminary subject to change without notice electrical characteristics freescale semiconductor 8 3 electrical characteristics 3.1 introduction this section contains electrical and timing speci?ations for the MC9S08LL16 series of microcontrollers available at the time of publication. 3.2 parameter classi?ation the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding the following classi?ation is used and the parameters are tagged accordingly in the tables where appropriate: 39 29 pta0 kbip0 ss adp0 40 30 pta1 kbip1 spsck adp1 41 31 pta2 kbip2 sda miso adp2 42 32 pta3 kbip3 scl mosi adp3 43 33 pta4 kbip4 adp4 lcd31 44 34 pta5 kbip5 adp5 lcd30 45 35 lcd29 46 36 lcd28 47 37 lcd27 48 38 lcd26 49 39 lcd25 50 40 lcd24 51 lcd23 52 lcd22 53 lcd21 54 lcd20 55 lcd19 56 lcd18 57 lcd17 58 lcd16 59 41 pte7 lcd15 60 42 pte6 lcd14 61 43 pte5 lcd13 62 44 pte4 lcd12 63 45 pte3 lcd11 64 46 pte2 lcd10 table 2. pin availability by package pin-count <-- lowest priority --> highest 64 48 port pin alt 1 alt 2 alt3 alt4
electrical characteristics MC9S08LL16 series, rev. 3 preliminary subject to change without notice freescale semiconductor 9 note the classi?ation is shown in the column labeled ??in the parameter tables where appropriate. 3.3 absolute maximum ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the limits speci?d in table 4 may affect device reliability or cause permanent damage to the device. for functional operating conditions, refer to the remaining tables in this section. this device contains circuitry protecting against damage due to high static voltage or electrical ?lds; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either v ss or v dd ) or the programmable pull-up resistor associated with the pin is enabled. table 3. parameter classi?ations p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations. table 4. absolute maximum ratings rating symbol value unit supply voltage v dd ?.3 to +3.8 v maximum current into v dd i dd 120 ma digital input voltage v in ?.3 to v dd + 0.3 v instantaneous maximum current single pin limit (applies to all port pins) 1, 2, 3 1 input must be current limited to the value speci?d. to determine the value of the required current-limiting resistor, calculate resistance values for positive (v dd ) and negative (v ss ) clamp voltages, then use the larger of the two resistance values. 2 all functional non-supply pins, except for ptb2 are internally clamped to v ss and v dd . 3 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may ?w out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). i d 25 ma storage temperature range t stg ?5 to 150 c
MC9S08LL16 series, rev. 3 preliminary subject to change without notice electrical characteristics freescale semiconductor 10 3.4 thermal characteristics this section provides information about operating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the mcu design. to take p i/o into account in power calculations, determine the difference between actual pin voltage and v ss or v dd and multiply by the pin current for each i/o pin. except in cases of unusually high pin current (heavy loads), the difference between pin voltage and v ss or v dd will be very small. the average chip-junction temperature (t j ) in c can be obtained from: t j = t a + (p d ja ) eqn. 3-1 where: t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts ?chip internal power p i/o = power dissipation on input and output pins ?user determined for most applications, p i/o << p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k (t j + 273c) eqn. 3-2 solving equation 3-1 and equation 3-2 for k gives: k = p d (t a + 273c) + ja (p d ) 2 eqn. 3-3 table 5. thermal characteristics rating symbol value unit operating temperature range (packaged) t a t l to t h ?0 to 85 c maximum junction temperature t j 95 c thermal resistance single-layer board 64-pin lqfp ja 72 c/w 48-pin qfn 84 48-pin lqfp 81 thermal resistance four-layer board 64-pin lqfp ja 54 c/w 48-pin qfn 30 48-pin lqfp 57
electrical characteristics MC9S08LL16 series, rev. 3 preliminary subject to change without notice freescale semiconductor 11 where k is a constant pertaining to the particular part. k can be determined from equation 3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equation 3-1 and equation 3-2 iteratively for any value of t a . 3.5 esd protection and latch-up immunity although damage from electrostatic discharge (esd) is much less common on these devices than on early cmos circuits, normal handling precautions should be taken to avoid exposure to static discharge. quali?ation tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. all esd testing is in conformity with aec-q100 stress test quali?ation for automotive grade integrated circuits. during the device qualification, esd stresses were performed for the human body model (hbm), the machine model (mm) and the charge device model (cdm). a device is de?ed as a failure if after exposure to esd pulses the device no longer meets the device speci?ation. complete dc parametric and functional testing is performed per the applicable device speci?ation at room temperature followed by hot temperature, unless instructed otherwise in the device speci?ation. table 6. esd and latch-up test conditions model description symbol value unit human body model series resistance r1 1500 storage capacitance c 100 pf number of pulses per pin 3 charge device model series resistance r1 0 storage capacitance c 200 pf number of pulses per pin 3 latch-up minimum input voltage limit ?2.5 v maximum input voltage limit 7.5 v table 7. esd and latch-up protection characteristics no. rating 1 1 parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. symbol min max unit 1 human body model (hbm) v hbm 2000 v 2 charge device model (cdm) v cdm 500 v 3 latch-up current at t a = 85 ci lat 100 ma
MC9S08LL16 series, rev. 3 preliminary subject to change without notice electrical characteristics freescale semiconductor 12 3.6 dc characteristics this section includes information about power supply requirements and i/o pin characteristics. table 8. dc characteristics num c characteristic symbol condition min typ 1 max unit 1 operating voltage 1.8 3.6 v 2 c output high voltage pta[0:3], pta[6:7], ptb[0:7], ptc[0:7] 2 , low-drive strength v oh 1.8 v, i load = ? ma v dd ?0.5 v p pta[0:3], pta[6:7], ptb[0:7], ptc[0:7] 2 , high-drive strength 2.7 v, i load = ?0 ma v dd ?0.5 c 1.8 v, i load = ? ma v dd ?0.5 3 c output high voltage pta[4:5], ptd[0:7], pte[0:7], low-drive strength v oh 1.8 v, i load = ? ma v dd ?0.8 v p pta[4:5], ptd[0:7], pte[0:7], high-drive strength 2.7 v, i load = ? ma v dd ?0.8 c 1.8 v, i load = ? ma v dd ?0.5 4 d output high current max total i oh for all ports i oht 100 ma 5 c output low voltage pta[0:3], pta[6:7], ptb[0:7], ptc[0:7], low-drive strength v ol 1.8 v, i load = 2 ma 0.5 v p pta[0:3], pta[6:7], ptb[0:7], ptc[0:7], high-drive strength 2.7 v, i load = 10 ma 0.5 c 1.8 v, i load = 3 ma 0.5 6 c output low voltage pta[4:5], ptd[0:7], pte[0:7], low-drive strength v ol 1.8 v, i load = 1 ma 0.8 v p pta[4:5], ptd[0:7], pte[0:7], high-drive strength 2.7 v, i load = 5ma 0.8 c 1.8 v, i load = 1 ma 0.5 7d output low current max total i ol for all ports i olt 100 ma 8 p input high voltage all digital inputs v ih v dd > 2.7 v 0.70 x v dd v cv dd > 1.8 v 0.85 x v dd 9 p input low voltage all digital inputs v il v dd > 2.7 v 0.35 x v dd cv dd > 1.8 v 0.30 x v dd 10 c input hysteresis all digital inputs v hys 0.06 x v dd mv 11 p input leakage current all input only pins (per pin) |i in |v in = v dd or v ss 0.1 1 a 12 p hi-z (off-state) leakage current all input/output (per pin) |i oz |v in = v dd or v ss 0.1 1 a
electrical characteristics MC9S08LL16 series, rev. 3 preliminary subject to change without notice freescale semiconductor 13 table 9. all i/o pullup and pulldown typical resistor values (v dd = 3.0 v) 13 p pullup, pulldown resistors all digital inputs, when enabled r pu, r pd 17.5 52.5 k 14 d dc injection current 3, 4, 5 single pin limit i ic v in < v ss , v in > v dd ?.2 0.2 ma total mcu limit, includes sum of all stressed pins ? 5 ma 15 c input capacitance, all pins c in 8pf 16 c ram retention voltage v ram 0.6 1.0 v 17 c por re-arm voltage 6 v por 0.9 1.4 2.0 v 18 d por re-arm time t por 10 s 19 p low-voltage detection threshold v lv d v dd falling v dd rising 1.80 1.88 1.84 1.92 1.88 1.96 v 20 p low-voltage warning threshold v lv w v dd falling v dd rising 2.08 2.14 2.2 v 21 p low-voltage inhibit reset/recover hysteresis v hys ?0mv 22 p bandgap voltage reference 7 v bg 1.16 1.17 1.18 v 1 typical values are measured at 25 c. characterized, not tested 2 all i/o pins except for lcd pins in open drain mode. 3 all functional non-supply pins, except for ptb2 are internally clamped to v ss and v dd . 4 input must be current limited to the value speci?d. to determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 5 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if the positive injection current (v in >v dd ) is greater than i dd , the injection current may ?w out of v dd and could result in external power supply going out of regulation. ensure that external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 6 por will occur below the minimum voltage. 7 factory trimmed at v dd = 3.0 v, temp = 25 c table 8. dc characteristics (continued) num c characteristic symbol condition min typ 1 max unit pullup resistor typicals v dd (v) pull-up resistor (k ) 20 25 30 35 40 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 25c 85c ?0 c pulldown resistor typicals v dd (v) pulldown resistance (k ) 20 25 30 35 40 1.8 2.3 2.8 3.3 25c 85 c ?0 c 3.6 preliminary preliminary
MC9S08LL16 series, rev. 3 preliminary subject to change without notice electrical characteristics freescale semiconductor 14 table 10. typical low-side driver (sink) characteristics (non lcd pins) low drive (ptxdsn = 0) table 11. typical low-side driver (sink) characteristics(non lcd pins) high drive (ptxdsn = 1) table 12. typical high-side (source) characteristics (non lcd pins) low drive (ptxdsn = 0) typical v ol vs i ol at v dd = 3.0 v i ol (ma) v ol (v) 0 0.2 0.4 0.6 0.8 1 1.2 0 5 10 15 20 typical v ol vs v dd v dd (v) v ol (v) 0 0.05 0.1 0.15 0.2 1234 25c 85c ?0c 25 c, i ol = 2 ma 85 c, i ol = 2 ma ?0c, i ol = 2 ma preliminary preliminary typical v ol vs i ol at v dd = 3.0 v i ol (ma) v ol (v) 0 0.2 0.4 0.6 0.8 1 01 02 03 0 typical v ol vs v dd v dd (v) v ol (v) 0 0.1 0.2 0.3 0.4 1234 i ol = 6 ma i ol = 3 ma i ol = 10 ma 25c 85 c ?0 c 25c 85c ?0c preliminary preliminary typical v dd ?v oh vs i oh at v dd = 3.0 v i oh (ma)) 0 0.2 0.4 0.6 0.8 1 1.2 ?0 ?5 ?0 ? 0 typical v dd ?v oh vs v dd at spec i oh v dd (v) v dd ?v oh (v) 0 0.05 0.1 0.15 0.2 0.25 1234 v dd ?v oh (v) 25c 85 c ?0c 25 c, i oh = 2 ma 85c, i oh = 2 ma ?0 c, i oh = 2 ma preliminary preliminary
electrical characteristics MC9S08LL16 series, rev. 3 preliminary subject to change without notice freescale semiconductor 15 table 13. typical high-side (source) characteristics(non lcd pins) high drive (ptxdsn = 1) table 14. typical low-side driver (sink) characteristics (lcd/gpio pins) low drive (ptxdsn = 0) table 15. typical low-side driver (sink) characteristics(lcd/gpio pins) high drive (ptxdsn = 1) typical v dd ?v oh vs i oh at v dd = 3.0 v i oh (ma) 0 0.2 0.4 0.6 0.8 ?0 ?5 ?0 ?5 ?0 ? 0 typical v dd ?v oh vs v dd at spec i oh v dd (v) v dd ?v oh (v) 0 0.1 0.2 0.3 0.4 1234 i oh = ?0 ma i oh = ? ma i oh = ? ma v dd ?v oh (v) 25c 85c ?0 c 25c 85 c ?0 c preliminary preliminary typical v ol vs i ol at v dd = 3.0 v i ol (ma) v ol (v) 0 0.2 0.4 0.6 0.8 1 1.2 0 5 10 15 20 typical v ol vs v dd v dd (v) v ol (v) 0 0.05 0.1 0.15 0.2 1234 25c 85 c ?0c 25c, i ol = 2 ma 85c, i ol = 2 ma ?0 c, i ol = 2 ma preliminary preliminary typical v ol vs i ol at v dd = 3.0 v i ol (ma) v ol (v) 0 0.2 0.4 0.6 0.8 1 01 02 03 0 typical v ol vs v dd v dd (v) v ol (v) 0 0.1 0.2 0.3 0.4 1234 i ol = 6 ma i ol = 3 ma i ol = 10 ma 25c 85c ?0 c 25c 85c ?0c preliminary preliminary
MC9S08LL16 series, rev. 3 preliminary subject to change without notice electrical characteristics freescale semiconductor 16 table 16. typical high-side (source) characteristics (lcd/gpio pins) low drive (ptxdsn = 0) table 17. typical high-side (source) characteristics(lcd/gpio pins) high drive (ptxdsn = 1) 3.7 supply current characteristics this section includes information about power supply current in various operating modes. table 18. supply current characteristics num c parameter symbol bus freq v dd (v) typ 1 max unit temp ( c) 1 p run supply current fei mode, all modules on ri dd 8 mhz 3 5.60 5.70 ma ?0 to 85 c t 1 mhz 1 1.52 2 t run supply current fei mode, all modules off ri dd 10 mhz 3 3.60 ma ?0 to 85 c t 1 mhz 0.50 3 t run supply current lprs=0, all modules off ri dd 16 khz fbilp 3 165 a ?0 to 85 c t 16 khz fbelp 105 4 t run supply current lprs=1, all modules off; running from flash ri dd 16 khz fbilp 377 a ?0 to 85 c t 16 khz fbelp 21 typical v dd ?v oh vs i oh at v dd = 3.0 v i oh (ma)) 0 0.2 0.4 0.6 0.8 1 1.2 ?0 ?5 ?0 ? 0 typical v dd ?v oh vs v dd at spec i oh v dd (v) v dd ?v oh (v) 0 0.05 0.1 0.15 0.2 0.25 1234 v dd ?v oh (v) 25c 85 c ?0c 25 c, i oh = 2 ma 85c, i oh = 2 ma ?0 c, i oh = 2 ma preliminary preliminary typical v dd ?v oh vs i oh at v dd = 3.0 v i oh (ma) 0 0.2 0.4 0.6 0.8 ?0 ?5 ?0 ?5 ?0 ? 0 typical v dd ?v oh vs v dd at spec i oh v dd (v) v dd ?v oh (v) 0 0.1 0.2 0.3 0.4 1234 i oh = ?0 ma i oh = ? ma i oh = ? ma v dd ?v oh (v) 25c 85c ?0 c 25c 85 c ?0 c preliminary preliminary
electrical characteristics MC9S08LL16 series, rev. 3 preliminary subject to change without notice freescale semiconductor 17 5 t run supply current lprs=1, all modules off; running from ram ri dd 16 khz fbilp 377 a ?0 to 85 c t 16 khz fbelp 7.3 6 p wait mode supply current fei mode, all modules off wi dd 8 mhz 3 2.3 3.5 ma ?0 to 85 c c 1 mhz 0.8 1.15 7 wait mode supply current lprs = 1, all modules off wi dd 16 khz fbelp 3 1.3 a ?0 to 85 c 8 p stop2 mode supply current s2i dd n/a 3 tbd tbd na ?0 to 25 c tbd tbd ?0 to 70 c 300 8500 ?0 to 85 c c n/a 2 tbd tbd ?0 to 25 c tbd tbd ?0 to 70 c 250 7700 ?0 to 85 c 9 p stop3 mode supply current no clocks active s3i dd n/a 3 tbd tbd na ?0 to 25 c tbd tbd ?0 to 70 c 400 12300 ?0 to 85 c c n/a 2 tbd tbd ?0 to 25 c tbd tbd ?0 to 70 c 350 11500 ?0 to 85 c 1 typical values are measured at 25 c. characterized, not tested. table 19. stop mode adders num c parameter condition temperature ( c) units -40 25 70 85 1 t lpo tbd tbd tbd tbd na 2 t errefsten range = hgo = 0 tbd tbd tbd tbd na 3 t irefsten 1 1 not available in stop2 mode. tbd tbd tbd tbd ua 4 t tod does not include clock source current tbd tbd tbd tbd na 5 tlvd 1 lvdse = 1 tbd tbd tbd tbd ua 6 t acmp 1 not using the bandgap (bgbe = 0) tbd tbd tbd tbd ua 7 t adc 1 adlpc = adlsmp = 1 not using the bandgap (bgbe = 0) tbd tbd tbd tbd ua table 18. supply current characteristics num c parameter symbol bus freq v dd (v) typ 1 max unit temp ( c)
MC9S08LL16 series, rev. 3 preliminary subject to change without notice electrical characteristics freescale semiconductor 18 figure 4. typical run i dd for fbe and fei, i dd vs. v dd (acmp and adc off, all other modules enabled) tbd
electrical characteristics MC9S08LL16 series, rev. 3 preliminary subject to change without notice freescale semiconductor 19 3.8 external oscillator (xoscvlp) characteristics reference figure 5 and figure 6 for crystal or resonator circuits. table 20. xoscvlp and ics speci?ations (temperature range = ?0 to 85 c ambient) num c characteristic symbol min typ 1 1 data in typical column was characterized at 3.0 v, 25 c or is typical recommended value. max unit 1 c oscillator crystal or resonator (erefs = 1, erclken = 1) low range (range = 0) high range (range = 1), high gain (hgo = 1) high range (range = 1), low power (hgo = 0) f lo f hi f hi 32 1 1 38.4 16 8 khz mhz mhz 2 d load capacitors low range (range=0), low power (hgo=0) other oscillator settings c 1, c 2 see note 2 see note 3 2 load capacitors ( c 1, c 2 ), feedback resistor ( r f ) and series resistor ( r s ) are incorporated internally when range=hgo=0. 3 see crystal or resonator manufacturers recommendation. 3 d feedback resistor low range, low power (range=0, hgo=0) 2 low range, high gain (range=0, hgo=1) high range (range=1, hgo=x) r f 10 1 m 4 d series resistor low range, low power (range = 0, hgo = 0) 2 low range, high gain (range = 0, hgo = 1) high range, low power (range = 1, hgo = 0) high range, high gain (range = 1, hgo = 1) 8 mhz 4 mhz 1 mhz r s 100 0 0 0 0 0 10 20 k 5 c crystal start-up time 4 low range, low power low range, high gain high range, low power high range, high gain 4 proper pc board layout procedures must be followed to achieve speci?ations. t cstl t csth 600 400 5 15 ms 6 d square wave input clock frequency (erefs = 0, erclken = 1) fee mode fbe or fbelp mode f extal 0.03125 0 20 20 mhz mhz
MC9S08LL16 series, rev. 3 preliminary subject to change without notice electrical characteristics freescale semiconductor 20 figure 5. typical crystal or resonator circuit: high range and low range/high gain figure 6. typical crystal or resonator circuit: low range/low power 3.9 internal clock source (ics) characteristics table 21. ics frequency speci?ations (temperature range = ?0 to 85 c ambient) num c characteristic symbol min typ 1 max unit 1 p average internal reference frequency ?factory trimmed at vdd = 3.6 v and temperature = 25 c f int_ft 32.768 khz 2 p average internal reference frequency - trimmed f int_t 31.25 39.063 khz 3 t internal reference start-up time t irst 6 s 4 p dco output frequency range - untrimmed f dco_ut 12.8 16.8 21.33 mhz 5 p dco output frequency range - trimmed f dco_t 16 20 mhz 6c resolution of trimmed dco output frequency at ?ed voltage and temperature (using ftrim) f dco_res_t 0.1 0.2 %f dco 7c resolution of trimmed dco output frequency at ?ed voltage and temperature (not using ftrim) f dco_res_t 0.2 0.4 %f dco 8c total deviation from trimmed dco output frequency over voltage and temperature f dco_t + 0.5 -1.0 2 %f dco xoscvlp extal xtal crystal or resonator r s c 2 r f c 1 xoscvlp extal xtal crystal or resonator
electrical characteristics MC9S08LL16 series, rev. 3 preliminary subject to change without notice freescale semiconductor 21 figure 7. deviation of dco output from trimmed frequency (20 mhz, 3.0 v) 9c total deviation from trimmed dco output frequency over ?ed voltage and temperature range of 0 c to 70 c f dco_t 0.5 1 %f dco 10 c fll acquisition time 2 t acquire 1ms 11 c long term jitter of dco output clock (averaged over 2-ms interval) 3 c jitter 0.02 0.2 %f dco 1 data in typical column was characterized at 3.0 v, 25 c or is typical recommended value. 2 this speci?ation applies to any time the fll reference source or reference divider is changed, trim value changed or changing from fll disabled (fbelp, fbilp) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this speci?ation assumes it is already running. 3 jitter is the average deviation from the programmed frequency measured over the speci?d interval at maximum f bus . measurements are made with the device powered by ?tered supplies and clocked by a stable external clock signal. noise injected into the fll circuitry via v dd and v ss and variation in the crystal oscillator frequency increase the c jitter percentage for a given interval. table 21. ics frequency speci?ations (temperature range = ?0 to 85 c ambient) (continued) num c characteristic symbol min typ 1 max unit tbd
MC9S08LL16 series, rev. 3 preliminary subject to change without notice electrical characteristics freescale semiconductor 22 figure 8. deviation of dco output from trimmed frequency (20 mhz, 25 c) tbd
electrical characteristics MC9S08LL16 series, rev. 3 preliminary subject to change without notice freescale semiconductor 23 3.10 ac characteristics this section describes timing characteristics for each peripheral system. 3.10.1 control timing figure 9. reset timing table 22. control timing num c rating symbol min typ 1 1 typical values are based on characterization data at v dd = 3.0v, 25 c unless otherwise stated. max unit 1d bus frequency (t cyc = 1/f bus )f bus dc 10 mhz 2 d internal low power oscillator period t lpo 700 1300 s 3d external reset pulse width 2 2 this is the shortest pulse that is guaranteed to be recognized as a reset pin request. t extrst 100 ns 4 d reset low drive t rstdrv 34 x t cyc ns 5d bkgd/ms setup time after issuing background debug force reset to enter user or bdm modes t mssu 500 ns 6d bkgd/ms hold time after issuing background debug force reset to enter user or bdm modes 3 3 to enter bdm mode following a por, bkgd/ms should be held low during the power-up and for a hold time of t msh after v dd rises above v lv d . t msh 100 s 7 d irq pulse width asynchronous path 2 synchronous path 4 4 this is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop mode, the synchronizer is bypassed so shorter pulses can be recognized. t ilih, t ihil 100 1.5 x t cyc ns 8 d keyboard interrupt pulse width asynchronous path 2 synchronous path 4 t ilih, t ihil 100 1.5 x t cyc ns 9 c port rise and fall time non-lcd pins low output drive (ptxds = 0) (load = 50 pf) 5, 6 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) 5 timing is shown with respect to 20% v dd and 80% v dd levels. temperature range ?0 c to 85 c. 6 except for lcd pins in open drain mode. t rise , t fall 16 23 ns port rise and fall time non-lcd pins high output drive (ptxds = 1) (load = 50 pf) 5, 6 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) t rise , t fall 5 9 ns t extrst reset pin
MC9S08LL16 series, rev. 3 preliminary subject to change without notice electrical characteristics freescale semiconductor 24 figure 10. irq/kbipx timing 3.10.2 tpm module timing synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. these synchronizers operate from the current bus rate clock. figure 11. timer external clock figure 12. timer input capture pulse table 23. tp input timing no. c function symbol min max unit 1 d external clock frequency f tclk 0f bus /4 hz 2 d external clock period t tclk 4t cyc 3 d external clock high time t clkh 1.5 t cyc 4 d external clock low time t clkl 1.5 t cyc 5 d input capture pulse width t icpw 1.5 t cyc t ihil irq/kbipx t ilih irq/kbipx t tclk t clkh t clkl tclk t icpw tpmchn t icpw tpmchn
electrical characteristics MC9S08LL16 series, rev. 3 preliminary subject to change without notice freescale semiconductor 25 3.10.3 spi timing table 24 and figure 13 through figure 16 describe the timing requirements for the spi system. table 24. spi timing no. c function symbol min max unit d operating frequency master slave f op f bus /2048 0 f bus /2 f bus /4 hz d spsck period master slave t spsck 2 4 2048 t cyc t cyc d enable lead time master slave t lead 1 /2 1 t spsck t cyc d enable lag time master slave t lag 1 /2 1 t spsck t cyc d clock (spsck) high or low time master slave t wspsck t cyc ?0 t cyc ?30 1024 t cyc ns ns d data setup time (inputs) master slave t su 15 15 ns ns d data hold time (inputs) master slave t hi 0 25 ns ns d slave access time t a ?t cyc d slave miso disable time t dis ?t cyc d data valid (after spsck edge) master slave t v 25 25 ns ns d data hold time (outputs) master slave t ho 0 0 ns ns d rise time input output t ri t ro t cyc ?25 25 ns ns d fall time input output t fi t fo t cyc ?25 25 ns ns 1 2 3 4 5 6 7 8 9 10 11 12
MC9S08LL16 series, rev. 3 preliminary subject to change without notice electrical characteristics freescale semiconductor 26 figure 13. spi master timing (cpha = 0) figure 14. spi master timing (cpha =1) spsck (output) spsck (output) miso (input) mosi (output) ss 1 (output) ms bin 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) notes: 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 1. ss output mode (dds7 = 1, ssoe = 1). 1 2 3 4 5 6 91 0 11 12 4 9 spsck (output) spsck (output) miso (input) mosi (output) msb in 2 bit 6 . . . 1 lsb in master msb out 2 master lsb out bit 6 . . . 1 port data (cpol = 0) (cpol = 1) port data ss 1 (output) 1. ss output mode (dds7 = 1, ssoe = 1). 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. notes: 2 1 12 11 3 4 4 11 12 5 6 9 10
electrical characteristics MC9S08LL16 series, rev. 3 preliminary subject to change without notice freescale semiconductor 27 figure 15. spi slave timing (cpha = 0) figure 16. spi slave timing (cpha = 1) spsck (input) spsck (input) mosi (input) miso (output) ss (input) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) note: slave see note 1 1. not defined but normally msb of character just received. 1 2 3 4 5 6 7 8 9 10 11 12 4 11 12 10 spsck (input) spsck (input) mosi (input) miso (output) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 see (cpol = 0) (cpol = 1) ss (input) note: slave note 1 1. not defined but normally lsb of character just received. 1 2 3 4 5 6 7 8 9 10 11 12 4 11 12
MC9S08LL16 series, rev. 3 preliminary subject to change without notice electrical characteristics freescale semiconductor 28 3.11 analog comparator (acmp) electricals 3.12 adc characteristics table 25. analog comparator electrical speci?ations c characteristic symbol min typical max unit d supply voltage v dd 1.8 3.6 v c supply current (active) i ddac ?035 a d analog input voltage v ain v ss ?0.3 v dd v p analog input offset voltage v aio 20 40 mv c analog comparator hysteresis v h 3.0 9.0 15.0 mv p analog input leakage current i alkg 1.0 a c analog comparator initialization delay t ainit 1.0 s table 26. 12-bit adc operating conditions characteristic conditions symb min typ 1 1 typical values assume v ddad = 3.0v, temp = 25 c, f adck =1.0mhz unless otherwise stated. typical values are for reference only and are not tested in production. max unit comment supply voltage absolute v ddad 1.8 3.6 v delta to v dd (v dd -v ddad ) 2 2 dc potential difference. v ddad -100 0 +100 mv ground voltage delta to v ss (v ss -v ssad ) 2 v ssad -100 0 +100 mv ref voltage high v refh 1.8 v ddad v ddad v input voltage v adin v refl ? refh v input capacitance c adin 4.5 5.5 pf input resistance r adin ? 7k analog source resistance 12 bit mode f adck > 4mhz f adck < 4mhz r as 2 5 k external to mcu 10 bit mode f adck > 4mhz f adck < 4mhz 5 10 8 bit mode (all valid f adck )1 0 adc conversion clock freq. high speed (adlpc=0) f adck 0.4 8.0 mhz low power (adlpc=1) 0.4 4.0
electrical characteristics MC9S08LL16 series, rev. 3 preliminary subject to change without notice freescale semiconductor 29 figure 17. adc input impedance equivalency diagram + + v as r as c as v adin z as pad leakage due to input protection z adin simplified input pin equivalent circuit r adin adc sar engine simplified channel select circuit input pin r adin c adin input pin r adin input pin r adin
MC9S08LL16 series, rev. 3 preliminary subject to change without notice electrical characteristics freescale semiconductor 30 table 27. 12-bit adc characteristics (v refh = v ddad , v refl = v ssad ) c characteristic conditions symb min typ 1 max unit comment t supply current adlpc=1 adlsmp=1 adco=1 i ddad 120 a t supply current adlpc=1 adlsmp=0 adco=1 i ddad 200 a t supply current adlpc=0 adlsmp=1 adco=1 i ddad 290 a p supply current adlpc=0 adlsmp=0 adco=1 i ddad 0.53 1 ma p adc asynchronous clock source high speed (adlpc=0) f adack 2 3.3 5 mhz t adack = 1/f adack c low power (adlpc=1) 1.25 2 3.3 p conversion time (including sample time) short sample (adlsmp=0) t adc 20 adck cycles see adc chapter in the ll16 reference manual for conversion time variances c long sample (adlsmp=1) 40 p sample time short sample (adlsmp=0) t ads 3.5 adck cycles c long sample (adlsmp=1) 23.5 t total unadjusted error 12 bit mode e tue 3.0 lsb 2 includes quantization p 10 bit mode 1 2.5 t 8 bit mode 0.5 1.0 t differential non-linearity 12 bit mode dnl 1.75 lsb 2 p 10 bit mode 3 0.5 1.0 t 8 bit mode 3 0.3 0.5 t integral non-linearity 12 bit mode inl 1.5 lsb 2 p 10 bit mode 0.5 1.0 t 8 bit mode 0.3 0.5 t zero-scale error 12 bit mode e zs 1.5 lsb 2 v adin = v ssad p 10 bit mode 0.5 1.5 t 8 bit mode 0.5 0.5
electrical characteristics MC9S08LL16 series, rev. 3 preliminary subject to change without notice freescale semiconductor 31 t full-scale error 12 bit mode e fs 1.0 lsb 2 v adin =v ddad p 10 bit mode 0.5 1 t 8 bit mode 0.5 0.5 d quantization error 12 bit mode e q -1 to 0 lsb 2 10 bit mode 0.5 8 bit mode 0.5 d input leakage error 12 bit mode e il 2 lsb 2 pad leakage 4 * r as 10 bit mode 0.2 4 8 bit mode 0.1 1.2 d temp sensor slope -40 c to 25c m 1.646 mv/ c 25 c to 85 c 1.769 d temp sensor voltage 25 cv temp25 701.2 mv 1 typical values assume v ddad = 3.0v, temp = 25 c, f adck =1.0mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2 1 lsb = (v refh - v refl )/2 n 3 monotonicity and no-missing-codes guaranteed in 10 bit and 8 bit modes 4 based on input pad leakage current. refer to pad electricals. table 27. 12-bit adc characteristics (v refh = v ddad , v refl = v ssad ) (continued) c characteristic conditions symb min typ 1 max unit comment
MC9S08LL16 series, rev. 3 preliminary subject to change without notice electrical characteristics freescale semiconductor 32 3.13 lcd speci?ations 3.14 flash speci?ations this section provides details about program/erase times and program-erase endurance for the flash memory. program and erase operations do not require any special power sources other than the normal v dd supply. for more detailed information about program/erase operations, see the memory section. table 28. lcd electricals, 3-v glass c characteristic symbol min typ max unit d lcd supply voltage v lcd .9 1.5 1.8 v d lcd frame frequency f frame 28 30 58 hz d lcd charge pump capacitance c lcd 100 100 nf d lcd bypass capacitance c bylcd 100 100 nf d lcd glass capacitance c glass 2000 8000 pf dv ireg hrefsel = 0 v ireg .89 1.00 1.15 v hrefsel = 1 1.49 1.67 1.85 1 1 v ireg max can not exceed v dd -0.15 v dv ireg trim resolution rtrim 1.5 % v ireg dv ireg ripple hrefsel = 0 .1 v hrefsel = 1 .15 dv lcd buffered adder 2 2 vsupply = 10, bypass = 0 i buff 1 a
electrical characteristics MC9S08LL16 series, rev. 3 preliminary subject to change without notice freescale semiconductor 33 3.15 emc performance electromagnetic compatibility (emc) performance is highly dependant on the environment in which the mcu resides. board design and layout, circuit topology choices, location and characteristics of external components as well as mcu software operation all play a signi?ant role in emc performance. the system designer should consult freescale applications notes such as an2321, an1050, an1263, an2764, and an1259 for advice and guidance speci?ally targeted at optimizing emc performance. 3.15.1 radiated emissions microcontroller radiated rf emissions are measured from 150 khz to 1 ghz using the tem/gtem cell method in accordance with the iec 61967-2 and sae j1752/3 standards. the measurement is performed with the microcontroller installed on a custom emc evaluation board while running specialized emc test software. the radiated emissions from the microcontroller are measured in a tem cell in two package orientations (north and east). table 29. flash characteristics c characteristic symbol min typical max unit d supply voltage for program/erase -40 c to 85 cv prog/erase 1.8 3.6 v d supply voltage for read operation v read 1.8 3.6 v d internal fclk frequency 1 1 the frequency of this clock is controlled by a software setting. f fclk 150 200 khz d internal fclk period (1/fclk) t fcyc 5 6.67 s p byte program time (random location) 2 t prog 9t fcyc p byte program time (burst mode) 2 t burst 4t fcyc p page erase time 2 2 these values are hardware state machine controlled. user code does not need to count cycles. this information supplied for calculating approximate time to program and erase. t page 4000 t fcyc p mass erase time 2 t mass 20,000 t fcyc d byte program current 3 3 the program and erase currents are additional to the standard run i dd . these values are measured at room temperatures with v dd = 3.0 v, bus frequency = 4.0 mhz. r iddbp ?m a d page erase current 3 r iddpe ?m a c program/erase endurance 4 t l to t h = ?0c to + 85c t = 25c 4 typical endurance for flash was evaluated for this product family on the 9s12dx64. for additional information on how freescale de?es typical endurance, please refer to engineering bulletin eb619, typical endurance for nonvolatile memory . 10,000 100,000 cycles c data retention 5 5 typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 c using the arrhenius equation. for additional information on how freescale de?es typical data retention, please refer to engineering bulletin eb618, typical data retention for nonvolatile memory. t d_ret 15 100 years
MC9S08LL16 series, rev. 3 preliminary subject to change without notice ordering information freescale semiconductor 34 the maximum radiated rf emissions of the tested con?uration in all orientations are less than or equal to the reported emissions levels. the susceptibility performance classi?ation is described in table 31 . 4 ordering information this section contains the ordering information and the device numbering system for the MC9S08LL16 series. table 30. radiated emissions, electric field parameter symbol conditions frequency f osc /f bus level 1 (max) 1 data based on quali?ation test results. unit radiated emissions, electric ?ld v re_tem v dd = 3.3 v t a = +25 o c package type 64-pin lqfp 0.15 ?50 mhz 32 khz crystal 10 mhz bus ? dbv 50 ?150 mhz ? 150 ?500 mhz ? 500 ?1000 mhz ? iec level n sae level 1 table 31. susceptibility performance classi?ation result performance criteria a no failure the mcu performs as designed during and after exposure. b self-recovering failure the mcu does not perform as designed during exposure. the mcu returns automatically to normal operation after exposure is removed. c soft failure the mcu does not perform as designed during exposure. the mcu does not return to normal operation until exposure is removed and the reset pin is asserted. d hard failure the mcu does not perform as designed during exposure. the mcu does not return to normal operation until exposure is removed and the power to the mcu is cycled. e damage the mcu does not perform as designed during and after exposure. the mcu cannot be returned to proper operation due to physical damage or other permanent performance degradation.
package information and mechanical drawings MC9S08LL16 series, rev. 3 preliminary subject to change without notice freescale semiconductor 35 4.1 device numbering system example of the device numbering system: 5 package information and mechanical drawings table 32 provides the available package types and their document numbers. the latest package outline/mechanical drawings are available on the MC9S08LL16 series product summary pages at http://www.freescale.com . to view the latest drawing, either: click on the appropriate link in table 32 , or open a browser to the freescale website ( http://www.freescale.com), and enter the appropriate document number (from table 32 ) in the ?nter keyword?search box at the top of the page. table 32. package descriptions pin count package type abbreviation designator case no. document no. 64 low quad flat package lqfp lh 840f 98ass23234w 48 low quad flat package lqfp lf 932 98ash00962a 48 quad flat no-leads qfn gt 1314 98arh99048a mc temperature range family memory status core (c = ?0 c to 85c) (9 = flash-based) 9 s08 xx (mc = fully qualified) package designator (see ta bl e 3 2 ) approximate flash size in kbytes ll 16 c
document number: MC9S08LL16 rev. 3 01/2009 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/paci?: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and speci?ally disclaims any and all liability, including without limitation consequential or incidental damages. ?ypical?parameters that may be provided in freescale semiconductor data sheets and/or speci?ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?ypicals? must be validated for each customer application by customers technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its of?ers, employees, subsidiaries, af?iates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ?freescale semiconductor, inc. 2009. all rights reserved. preliminary subject to change without notice

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